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About
Insights
Manual
FAQ
Release Notes
Screencasts
Tech Articles
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Linting rules
Insights
Manual
Setting Up Sigasi Studio
Setting Up a Project
Libraries
User Interface
Views
Sigasi Studio Editor
Mixed language projects
Opening Files
Linting and Quick Fixes
Verilog and SystemVerilog Linting
VHDL Linting
Tool Integration
Sigasi Studio VUnit Integration
Documentation Generation
Graphics Configuration
Third party plugins
Troubleshooting
Keyboard Shortcuts
Configuring Your Design Environment
License Key Management
Sigasi Studio Talkback
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Release Notes
Sigasi Studio 4.9
Sigasi Studio 4.8
Sigasi Studio 4.7
Sigasi Studio 4.6
Sigasi Studio 4.5
Sigasi Studio 4.4
Sigasi Studio 4.3
Sigasi Studio 4.2
Sigasi Studio 4.1
Sigasi Studio 4.0
Sigasi Studio 3
Sigasi Studio 2
Screencasts
Tech Articles
Opinion
These chapters contain detailed explanations for the various linting rules.
Capitalization of Identifiers
Check for component/entity mismatch
Check header comment
Check that filename contains primary unit name
Dead Code lint
Deprecated IEEE Packages, Non-Standard Packages
Incomplete Port Maps and Generic Maps
Linting rules for loops
Naming Conventions
Null Range (empty range)
Order of associations
Positional Association in Instantiations
Quick Fix for Third Party Libraries
Redundant "others"
Sensitivity List
Space Before the Physical Unit
Superfluous Library Clause
Testing equality of booleans to true or false
Vector width in assignments and port maps
Verilog assignment patterns
Verilog case statements
Verilog checks on initialization
Verilog coding style
Verilog functions
Verilog identifiers
Verilog inputs
Verilog keywords in VHDL
Verilog parameters
Verilog port and parameter associations
Verilog processes
Verilog reg and logic datatype
The
Sigasi Studio Manual on a single page
is ideal for saving or printing to PDF.
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