These chapters contain detailed explanations for the various linting rules.
- Capitalization of Identifiers
- Check for Component/Entity Mismatch
- Check Header Comment
- Dead Code Linting Rule
- Deprecated IEEE Packages and Non-Standard Packages
- Filename Contains Primary Unit Name
- Incomplete Port Maps and Generic Maps
- Linting Rules for Arrays
- Linting Rules for Instances
- Linting Rules for Loops
- Naming Conventions
- Null or Empty Range
- Order of Associations
- Positional Association in Instantiations
- Quick Fix for Third-Party Libraries
- Redundant "others"
- Sensitivity List
- Space Before the Physical Unit
- Superfluous Library Clause
- Testing Equality of Booleans to true or false
- Types in Expressions
- Vector Width in Assignments and Port Maps
- Verilog Ambiguous Reference
- Verilog Assignment Patterns
- Verilog Case Statements
- Verilog Checks on Initialization
- Verilog Class Item Visibility
- Verilog Coding Style
- Verilog Duplicate Declaration
- Verilog Functions
- Verilog Identifiers and Data Types
- Verilog Inputs
- Verilog Keywords in VHDL
- Verilog Out-of-bound Method Declarations
- Verilog Overridden Method Signatures
- Verilog Parameters
- Verilog Port and Parameter Associations
- Verilog Processes
- Verilog reg and logic Datatype
- VHDL Coding Style Rules
- VHDL Language Version
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