These chapters contain detailed explanations for the various linting rules.
- Capitalization of Identifiers
- Check for component/entity mismatch
- Check header comment
- Check that filename contains primary unit name
- Dead Code lint
- Deprecated IEEE Packages, Non-Standard Packages
- Incomplete Port Maps and Generic Maps
- Linting rules for loops
- Naming Conventions
- Null Range (empty range)
- Order of associations
- Positional Association in Instantiations
- Quick Fix for Third Party Libraries
- Redundant "others"
- Sensitivity List
- Space Before the Physical Unit
- Superfluous Library Clause
- Testing equality of booleans to true or false
- Vector width in assignments and port maps
- Verilog assignment patterns
- Verilog case statements
- Verilog checks on initialization
- Verilog coding style
- Verilog functions
- Verilog identifiers
- Verilog inputs
- Verilog keywords in VHDL
- Verilog parameters
- Verilog port and parameter associations
- Verilog processes
- Verilog reg and logic datatype
The Sigasi Studio Manual on a single page is ideal for saving or printing to PDF.