The main documentation on linting rules and how to configure them is available through the following links.
Sigasi Visual HDL
Sigasi Visual HDL for Eclipse
The following chapters contain detailed explanations for the various linting rules.
- Capitalization of Identifiers
- Case Alternative Contains Duplicate Choices
- Check for Component/Entity Mismatch
- Check Header Comment
- Clock Signal Not Used as Clock
- Comparison of Vectors with Different Sizes
- Dead Code Linting Rule
- Deep Nesting of Conditional and Loop Statements
- Deprecated IEEE Packages and Non-Standard Packages
- Deprecated UVM API
- End Name Does Not Match Declaration Name
- Filename Contains Primary Unit Name
- Implicit Vector to Boolean Conversion
- Incomplete Port Maps and Generic Maps
- Incomplete Reset Branch
- Inconsistent Clock Edge Usage
- Inconsistent Reset Style
- Incorrect Constructor for UVM Object or Component
- Incorrect Override of UVM Object
- Incorrect Utility Macro
- Incorrect UVM Object Instantiation
- Incorrect Vector Range Direction
- Language Feature Restrictions
- Linting Rules for Arrays
- Linting Rules for Deferred Constants
- Linting Rules for Design Unit Locations
- Linting Rules for Instances
- Linting Rules for Loops
- Missing include path in preprocessor configuration
- Missing Label
- Multiple Objects in One Declaration
- Naming Conventions
- Null or Empty Range
- Order of Associations
- Positional Association in Instantiations
- Prohibited Macro
- Redundant "others"
- Sensitivity List
- Space Before the Physical Unit
- Superfluous Library Clause
- Testing Equality of Booleans to true or false
- Tool Compatibility Rules
- Type Argument Value Does Not Match Containing Class
- Types in Expressions
- Unconstrained Signal or Variable of Integer Type
- Unexpected Clock Edge Specification
- Unexpected FSM State Type
- Unexpected Keyword Capitalization
- Unexpected Output System Task
- Unregistered UVM Object
- UVM Object Name Does Not Match Variable Name
- UVM Phase Method Does Not Call Superclass Method
- Vector as Edge Event Expression
- Vector Width in Assignments and Port Maps
- Verilog Ambiguous Reference
- Verilog Assignment Patterns
- Verilog Case Statements
- Verilog Checks on Initialization
- Verilog Class Item Visibility
- Verilog Coding Style
- Verilog Duplicate Conditions
- Verilog Duplicate Continuous Assignments
- Verilog Duplicate Declaration
- Verilog Duplicate Port
- Verilog Empty Assignment Pattern
- Verilog Empty Concatenation
- Verilog Empty Parameters
- Verilog Empty Port
- Verilog Empty Port in ANSI Port List
- Verilog Functions
- Verilog Hiding Non-virtual Methods
- Verilog Identifiers and Data Types
- Verilog Implicit Net
- Verilog Incorrect Port Declaration
- Verilog Inputs
- Verilog Keywords in VHDL
- Verilog Out-of-bound Method Declarations
- Verilog Overridden Method Signatures
- Verilog Parameters
- Verilog Port and Parameter Associations
- Verilog Processes
- Verilog reg and logic Datatype
- Verilog Type Checking
- Verilog Unused Declaration
- Verilog Unused Macros
- Verilog Upward Reference
- VHDL Coding Style Rules
- VHDL Language Version