Your work with Sigasi Studio typically is organized as a project. A project is a collection of VHDL and/or (System)Verilog files that belong together. Sigasi Studio understands the HDL units defined in the files, and the relationships between them.
Your first step is to set up a project. There are a number of ways to do this. The most common ways are:
Mixed language projects
Note that while you initially need to choose between a VHDL and a (System)Verilog project, any Sigasi Studio project can be a mixed language project. If you wish to create a mixed language project, we recommend to import or create a VHDL project and then add the (System)Verilog support to this project.
To create a mixed language project, right click your project and select Configure > Add VHDL support or Configure > Add (System)Verilog support as needed.
In projects you can navigate from instantiation statements to the matching entity or module. This also works in mixed language projects. You can navigate from VHDL entity instantiations in (System)Verilog code and (System)Verilog module instantiations in VHDL code. You can also open the declaration of ports and generics/parameters in mixed instantiations.
Other supported features:
- Find references for entity names, modules, ports, generics and parameters.
- Autocomplete (System)Verilog module instantiations in VHDL code and VHDL entity instantiations in (System)Verilog code.
- Error reporting of incorrect entity names, modules, ports, generics and parameters in instantiations.
- renames of signals and ports.
Screencast : Mixed languages: instantiating Verilog in VHDL code
Importing a project from the file system
1: Import the project
You can import an existing VHDL or (System)Verilog project from the file system by clicking File > Import… > Sigasi > Import a VHDL project or Import a (System)Verilog project. Browse to the root directory of the project, and press Finish.
2: Set Libraries (VHDL or Mixed)
Since Sigasi Studio 4.4, Sigasi Studio automatically configures libraries of imported projects, based on project information
use clauses. If you need to customize the library configuration, you can assign different
libraries to your files and folders. Right-click on a file or folder and select Library Mapping > New Library….
Then fill out the correct library name.
The following chapter gives more information on using libraries.
3: Add any files that are in other directories
If you need additional files that are not in the project root directory, just drag them from your Windows Explorer (or other file browser) into the project. You will have the option to create a link rather than copying the files.
Note 1: dragging files works on Windows (using Windows Explorer), on Mac OS X (using Finder) and on Linux (using Gnome Nautilus). If you use KDE, you should install Nautilus.
Note 2: to avoid absolute paths in the .project file, environment variables can be used.
Right-click the file or directory in the project explorer and select
Properties > Resource > Location > Edit… to configure the path of the resource.
To access environment variables, you have to prefix the environment variable with
For example: to refer to the home directory you can use
Creating a new, empty project
To create a new project, select File > New > VHDL Project or File > New > (System)Verilog Project. Then give your project a name.
By default, the Use default location checkbox is checked, which means that new projects will be located in the workspace folder. Alternatively, you can uncheck the checkbox and choose an arbitrary location for your project. This is especially useful if you want to use Sigasi Studio with an existing design.
You can also select the VHDL version or the version of
After creating a new project, you can add existing files by dragging them from your filesystem into the project explorer. New files can be added by clicking File > New > VHDL file, File > New > Verilog file or File > New > SystemVerilog file.
Other ways to set up a project
Adding VHDL or Verilog support to an existing Eclipse project
You can also add VHDL or Verilog support to any project in your workspace by right-clicking the project in the project explorer and selecting Configure > Add VHDL support or Configure > Add (System)Verilog support. You can also remove VHDL or Verilog support from Sigasi Studio projects by selecting Configure > Remove VHDL support or Configure > Remove (System)Verilog support.
Note that with a Sigasi Studio XL or a Sigasi Studio XPRT license, you can have mixed VHDL and Verilog support at the same time.
Importing a project from an archive
Sigasi Studio projects can be shared using file archives. All project-related settings are stored in two hidden files in the project folder. Therefore, you can create an archive of the entire top level folder (File > Export > General > Archive file) and send it to someone else.
You can import a project from an archive by clicking File > Import… > General > Existing projects into Workspace and selecting Select archive file. Browse to your project archive and press Finish.
Programatically creating a project
The Sigasi Studio
.library_mapping.xml files can be created using code from our
publicly available Sigasi Project Creator project.
The project offers Python classes that make it easy to generate a Sigasi Project from your own project specifications. For more information and examples, check out the Sigasi Project Creator project on GitHub.