VHDL Linting

List of VHDL code rules

The table below lists the VHDL code rules that can be checked automatically by Sigasi Studio. The availability of code rules depends on the license requirements.

ST code rules

ST code rules are available for all licenses including Sigasi Studio Starter .

Description ID
Warning with lightbulb Declaration could not be found
Duplicate declarations
Warning with lightbulb Signal/variable assignment operator
Warning with lightbulb Case statement does not cover all choices
Warning with lightbulb Missing enumeration literal in case statements
Instantiation statement validation
Library validation
Subprograms in packages (e.g. function body in a package, rather than in the package body)
Missing return statement in function bodies
Warning with lightbulb Correct attribute entity class in attribute specifications
Warning with lightbulb C-style equality and inequality operator (= and /= vs == and !=)
Warning with lightbulb VHDL 2008 features in VHDL 93 mode (Learn about choosing your VHDL version)
Warning with lightbulb Port/Generic lists cannot be terminated with a ‘;’
Warning with lightbulb Port/Generic maps cannot be terminated with a ‘,’

XL code rules

XL code rules require a Sigasi Studio XL or Sigasi Studio XPRT license.

Description ID
Null range: The left argument is strictly larger than the right 1
Warning with lightbulb Deprecated IEEE packages 8
Case alternative contains redundant choices 12
Case statement contains all choices explicitly. You can safely remove the redundant ‘others’ 13
Infinite loop. Loop is missing a wait 20
Null range: The left argument is strictly smaller than the right 26
Warning with lightbulb Non-standard packages 37
Warning with lightbulb A process must either have a sensitivity list or contain one or more wait statements 38
There has to be a whitespace before physical units 47
Unbound component instantiations 48
Superfluous library clause 49
Warning with lightbulb Library is not available Configure Altera, Xilinx, ModelSim and VUnit libraries 50
Warning with lightbulb Find unused declarations 55
Bitstrings may only contain std_logic metavalues 57
Duplicate, conflicting design unit names 64
Find unused ports 67
Find unused generics 68
Find dead states in state machines 71
Warning with lightbulb Find incomplete sensitivity lists 72
Find superfluous signals in sensitivity lists 73
Find dead code (unreachable statements) 79
Report encrypted files 84
Find duplicate signals in sensitivity lists 85
Detect signals and variables that are never written 88
Detect signals and variables that are never read 89
None or multiple matching entities for component 90
Check naming conventions 92
Warning with lightbulb Incomplete port map or generic map 94
Vector width in assignments and port maps 144
Warning with lightbulb All references must have the same capitalization as their declaration 163
Warning with lightbulb Check for positional associations in instantiations 164
Invalid port associations (incompatible port modes in instantiations) 169
Warning with lightbulb Order of generic and port associations 177
Incorrect component name in configuration 180
Incorrect instantiation statement label in configuration 181
Missing or incorrect binding indication 182
Incorrect name in binding indication 183
Incorrect use of keyword all 184
Redundant boolean equality check with true 185
Boolean equality check with false 186
Warning with lightbulb Check for component/entity mismatch 187
Header comment check 188
Filename must contain primary unit name 189
Empty loop statement 190
Entity name is a Verilog or SystemVerilog keyword 192
Instantiation mismatch 198
Circular compilation dependency 203
Type declaration not allowed in expression 209
Index out of range 210
Slice has wrong direction 211
Unterminated string literal 215