VHDL Linting

List of VHDL code rules

The table below lists the VHDL code rules that can be checked automatically by Sigasi Studio. The availability of code rules depends on the license requirements.

ST code rules

ST code rules are available for all licenses including Sigasi Studio Starter .

Warning with lightbulbDeclaration could not be found
Duplicate declarations
Warning with lightbulbSignal/variable assignment operator
Warning with lightbulbCase statement does not cover all choices
Warning with lightbulbMissing enumeration literal in case statements
Instantiation statement validation
Library validation
Subprograms in packages (e.g. function body in a package, rather than in the package body)
Missing return statement in function bodies
Warning with lightbulbCorrect attribute entity class in attribute specifications
Warning with lightbulbC-style equality and inequality operator (= and /= vs == and !=)
Warning with lightbulbVHDL 2008 features in VHDL 93 mode (Learn about choosing your VHDL version)
Warning with lightbulbPort/Generic lists cannot be terminated with a ‘;’
Warning with lightbulbPort/Generic maps cannot be terminated with a ‘,’

XL code rules

XL code rules require a Sigasi Studio XL or Sigasi Studio XPRT license.

Null range: The left argument is strictly larger than the right1
Warning with lightbulbDeprecated IEEE packages8
Case alternative contains redundant choices12
Case statement contains all choices explicitly. You can safely remove the redundant ‘others’13
Infinite loop. Loop is missing a wait20
Null range: The left argument is strictly smaller than the right26
Warning with lightbulbNon-standard packages37
Warning with lightbulbA process must either have a sensitivity list or contain one or more wait statements38
There has to be a whitespace before physical units47
Unbound component instantiations48
Superfluous library clause49
Warning with lightbulbLibrary is not available Configure Altera, Xilinx, ModelSim and VUnit libraries50
Warning with lightbulbFind unused declarations55
Bitstrings may only contain std_logic metavalues57
Duplicate, conflicting design unit names64
Missing return statement in function body66
Find unused ports67
Find unused generics68
Find dead states in state machines71
Warning with lightbulbFind incomplete sensitivity lists72
Find superfluous signals in sensitivity lists73
Find dead code (unreachable statements)79
Report encrypted files84
Find duplicate signals in sensitivity lists85
Detect signals and variables that are never written88
Detect signals and variables that are never read89
None or multiple matching entities for component90
Check naming conventions92
Warning with lightbulbIncomplete port map or generic map94
Vector width in assignments and port maps144
Warning with lightbulbAll references must have the same capitalization as their declaration163
Warning with lightbulbCheck for positional associations in instantiations164
Invalid port associations (incompatible port modes in instantiations)169
VHDL version mismatch170
Warning with lightbulbOrder of generic and port associations177
Incorrect component name in configuration180
Incorrect instantiation statement label in configuration181
Missing or incorrect binding indication182
Incorrect name in binding indication183
Incorrect use of keyword all184
Redundant boolean equality check with true185
Boolean equality check with false186
Warning with lightbulbCheck for component/entity mismatch187
Header comment check188
Filename must contain primary unit name189
Empty loop statement190
Entity name is a Verilog or SystemVerilog keyword192
Instantiation mismatch198
Circular compilation dependency203
Type declaration not allowed in expression209
Index out of range210
Slice has wrong direction211
Unterminated string literal215