VHDL Linting

List of VHDL code rules

The table below lists the VHDL code rules that can be checked automatically by Sigasi Studio. The availability of code rules depends on the license requirements.

LicenseQuick FixDescriptionID
STDeclaration could not be found
STDuplicate declarations
STSignal/variable assignment operator
STCase statement does not cover all choices
STMissing enumeration literal in case statements
STInstantiation statement validation
STLibrary validation
STSubprograms in packages (e.g. function body in a package, rather than in the package body)
STMissing return statement in function bodies
STCorrect attribute entity class in attribute specifications
STC-style equality and inequality operator (= and /= vs == and !=)
STVHDL 2008 features in VHDL 93 mode (Learn about choosing your VHDL version)
STPort/Generic lists cannot be terminated with a ‘;’
STPort/Generic maps cannot be terminated with a ‘,’
CRDeprecated IEEE packages8
CRNon-standard packages37
CRA process must either have a sensitivity list or contain one or more wait statements38
CRThere has to be a whitespace before physical units47
CRSuperfluous library clause49
CRLibrary is not available Configure Altera, Xilinx, ModelSim and VUnit libraries50
CRFind unused declarations55
CRBitstrings may only contain std_logic metavalues57
CRDuplicate, conflicting design unit names64
CRFind unused ports67
CRFind unused generics68
CRFind incomplete sensitivity lists72
CRFind superfluous signals in sensitivity lists73
CRReport encrypted files84
CRFind duplicate signals in sensitivity lists85
CRIncorrect use of keyword all184
XLNull range: The left argument is strictly larger than the right1
XLCase alternative contains redundant choices12
XLCase statement contains all choices explicitly. You can safely remove the redundant ‘others’13
XLInfinite loop. Loop is missing a wait20
XLNull range: The left argument is strictly smaller than the right26
XLUnbound component instantiations48
XLFind dead states in state machines71
XLFind dead code (unreachable statements)79
XLDetect signals and variables that are never written88
XLDetect signals and variables that are never read89
XLNone or multiple matching entities for component90
XLCheck naming conventions92
XLIncomplete port map or generic map94
XLVector width in assignments and port maps144
XLAll references must have the same capitalization as their declaration163
XLCheck for positional associations in instantiations164
XLInvalid port associations (incompatible port modes in instantiations)169
XLOrder of generic and port associations177
XLIncorrect component name in configuration180
XLIncorrect instantiation statement label in configuration181
XLMissing or incorrect binding indication182
XLIncorrect name in binding indication183
XLRedundant boolean equality check with true185
XLBoolean equality check with false186
XLCheck for component/entity mismatch187
XLHeader comment check188
XLFilename must contain primary unit name189
XLEmpty loop statement190
XLEntity name is a Verilog or SystemVerilog keyword192