Verilog and SystemVerilog Linting

List of (System)Verilog code rules

The table below lists the (System)Verilog code rules that can be checked automatically by Sigasi Studio. The availability of code rules depends on the license requirements.

LicenseQuick FixDescriptionID
STFile encoding differences between including and included files
XLNull loops1
XLCheck Naming Conventions2
XLDisallow ‘reg’ datatype3
XLVHDL keyword as module name7