Verilog and SystemVerilog Linting

List of Verilog and SystemVerilog code rules

The table below lists the Verilog and SystemVerilog code rules that can be checked automatically by Sigasi Studio. The availability of code rules depends on the license requirements.

ST code rules

ST code rules are available for all licenses including Sigasi Studio Starter .

File encoding differences between including and included files
Named and positional port connections cannot be mixed5
The packed keyword is required in packed structs and unions6
The for loop statement misses mandatory part (Verilog)9
Parameter port list cannot be empty11
No semicolon expected at this point (Verilog)12
Verilog disallows empty assignments of ordered parameters (Verilog)13
Named and positional parameter overrides cannot be mixed25
Only one default member expression is allowed per assignment pattern29
Only variable output ports can have a default value in non-ANSI notation33
Only input or variable output ports can have a default value in ANSI notation34
Duplicate formal item within the instantiated unit37
Excessive number of actuals in ordered notation39
Timing controls are not allowed in functions46
Net data types must be 4-state50
Net data types integral51
Invalid package item55
Unexpected preprocessor directive inside design elements57
Non-packed member in packed structure59
Illegal type in untagged union60
Illegal class member access61
Declaration not found71
Attempted implicit declaration with default nettype none73
Invalid enumeration element range format74
Range of enumeration element is too large75
Invalid construct76
Invalid randomize argument77
Not a value expression78
Type not assignment compatible79
Constraint class scope missing80
Constraint class with packed dimensions81
Ambiguous reference93
Duplicate declaration95

XL code rules

XL code rules require a Sigasi Studio XL or Sigasi Studio XPRT license.

Empty loops and conditional branches1
Check naming conventions2
Warning with lightbulb Disallow reg datatype3
The module name is a keyword in VHDL and may cause problems in mixed language projects7
Case statement does not cover all cases8
Function prototype has implicit return type10
Info with lightbulb Implicit subprogram port direction14
Default clause has to be the last item in a case statement15
Case statement has multiple default clauses, but only one default clause is allowed16
File name does not match design unit17
File contains multiple design units18
Parameters must have a default value19
Verilog code line too long20
Tabs are not allowed21
File header comment does not match required pattern22
Named port connections have to be used for all instances with many ports24
Named parameter overrides have to be used for all instantiations with many parameters26
No event control at the top of always construct27
Default member must be last in assignment pattern28
Overwritten type key in assignment pattern30
Duplicate member key in structure assignment pattern31
Mixed named and ordered notation in assignment pattern32
Register initialization in declarations35
Formal item not found within the instantiated unit36
Missing actuals for formals that have no default value38
Default clause missing from case statement40
Non-blocking assignments are not allowed in functions41
Consecutive underscores in unit / port identifier42
Underscores at end of unit / port identifier43
Report encrypted regions44
Multiple statements per line47
Missing bit width for parameters wider than 32 bits48
Trailing comma is not recommended52
Empty parameter not allowed53
Empty parameter overrides not allowed54
Named connections are not allowed with blank ports56
Regular expressions (RE2/J) compatibility check58
Overridden method signature mismatch62-68
Local parameter has to be initialized69
Local parameter cannot be overridden70
Out-of-bound method signature mismatch82-92

Deprecated code rules

Deprecated code rules were used by Sigasi Studio at some point, but they’ve been removed or superseded in the most recent version.

A Verilog net type keyword cannot be followed directly by the reg keywordSuperseded by a syntax error4