List of (System)Verilog code rules
The table below lists the (System)Verilog code rules that can be checked automatically by Sigasi Studio. The availability of code rules depends on the license requirements.
- ST code rules are available for all licenses including Sigasi Studio Starter
- XL code rules require a Sigasi Studio XL license.
| License | Quick Fix | Description | ID |
|---|---|---|---|
| ST | File encoding differences between including and included files | ||
| XL | Null loops | 1 | |
| XL | Check Naming Conventions | 2 | |
| XL |  | Disallow ‘reg’ datatype | 3 |
| XL | VHDL keyword as module name | 7 |