The table below lists the (System)Verilog code rules that can be checked automatically by Sigasi Studio. The availability of code rules depends on the license requirements.
ST code rules are available for all licenses including Sigasi Studio Starter .
|File encoding differences between including and included files|
|Named and positional port connections cannot be mixed||5|
|Parameter port list cannot be empty||11|
|No semicolon expected at this point (Verilog)||12|
|Verilog disallows empty assignments of ordered parameters (Verilog)||13|
|Named and positional parameter overrides cannot be mixed||25|
|Only one default member expression is allowed per assignment pattern||29|
|Only variable output ports can have a default value in non-ANSI notation||33|
|Only input or variable output ports can have a default value in ANSI notation||34|
|Duplicate formal item within the instantiated unit||37|
|Excessive number of actuals in ordered notation||39|
|Timing controls are not allowed in functions||46|