List of Verilog and SystemVerilog code rules

The table below lists the Verilog and SystemVerilog code rules that can be checked automatically by Sigasi Studio. The availability of code rules depends on the license requirements.

ST code rules

ST code rules are available for all licenses including Sigasi Studio Starter .

	Description	ID
	File encoding differences between including and included files
	Named and positional port connections cannot be mixed	5
	The `packed` keyword is required in packed structs and unions	6
	The `for` loop statement misses mandatory part (Verilog)	9
	Parameter port list cannot be empty	11
	No semicolon expected at this point (Verilog)	12
	Verilog disallows empty assignments of ordered parameters (Verilog)	13
	Named and positional parameter overrides cannot be mixed	25
	Only one default member expression is allowed per assignment pattern	29
	Only variable output ports can have a default value in non-ANSI notation	33
	Only input or variable output ports can have a default value in ANSI notation	34
	Duplicate formal item within the instantiated unit	37
	Excessive number of actuals in ordered notation	39
	Timing controls are not allowed in functions	46
	Net data types must be 4-state	50
	Net data types integral	51
	Invalid package item	55
	Unexpected preprocessor directive inside design elements	57
	Non-packed member in packed structure	59
	Illegal type in untagged union	60
	Illegal class member access	61
	Declaration not found	71
	Attempted implicit declaration with default nettype none	73
	Invalid enumeration element range format	74
	Range of enumeration element is too large	75
	Invalid construct	76
	Invalid randomize argument	77
	Not a value expression	78
	Type not assignment compatible	79
	Constraint class scope missing	80
	Constraint class with packed dimensions	81
	Ambiguous reference	93
	Duplicate declaration	95

XL code rules

XL code rules require a Sigasi Studio XL or Sigasi Studio XPRT license.

	Description	ID
	Empty loops and conditional branches	1
	Check naming conventions	2
	Disallow `reg` datatype	3
	The module name is a keyword in VHDL and may cause problems in mixed language projects	7
	Case statement does not cover all cases	8
	Function prototype has implicit return type	10
	Implicit subprogram port direction	14
	Default clause has to be the last item in a case statement	15
	Case statement has multiple default clauses, but only one default clause is allowed	16
	File name does not match design unit	17
	File contains multiple design units	18
	Parameters must have a default value	19
	Verilog code line too long	20
	Tabs are not allowed	21
	File header comment does not match required pattern	22
	Named port connections have to be used for all instances with many ports	24
	Named parameter overrides have to be used for all instantiations with many parameters	26
	No event control at the top of `always` construct	27
	Default member must be last in assignment pattern	28
	Overwritten type key in assignment pattern	30
	Duplicate member key in structure assignment pattern	31
	Mixed named and ordered notation in assignment pattern	32
	Register initialization in declarations	35
	Formal item not found within the instantiated unit	36
	Missing actuals for formals that have no default value	38
	Default clause missing from case statement	40
	Non-blocking assignments are not allowed in functions	41
	Consecutive underscores in unit / port identifier	42
	Underscores at end of unit / port identifier	43
	Report encrypted regions	44
	Multiple statements per line	47
	Missing bit width for parameters wider than 32 bits	48
	Trailing comma is not recommended	52
	Empty parameter not allowed	53
	Empty parameter overrides not allowed	54
	Named connections are not allowed with blank ports	56
	Regular expressions (RE2/J) compatibility check	58
	Overridden method signature mismatch	62-68
	Local parameter has to be initialized	69
	Local parameter cannot be overridden	70
	Out-of-bound method signature mismatch	82-92

Deprecated code rules

Deprecated code rules were used by Sigasi Studio at some point, but they’ve been removed or superseded in the most recent version.

Description	Reason	ID
A Verilog `net` type keyword cannot be followed directly by the `reg` keyword	Superseded by a syntax error	4