VHDL Linting

List of VHDL Linting Rules

The table below lists the VHDL linting rules that can be checked automatically by Sigasi. The availability of linting rules depends on the license requirements.

ST Linting Rules

ST linting rules are available for all licenses including Sigasi Studio Starter .

error Positional associations order2
error ‘Others’ position in associations3
error Multiple others in associations4
error Input port cannot be assigned5
error Subprogram parameter cannot be assigned6
error Constant cannot be assigned7
error ‘others’ has to be the last alternative in a case statement9
error Only one ‘others’ choice is allowed10
error with lightbulb Case statement does not cover all cases11
error Case alternative contains duplicate choices14
error with lightbulb C style equality operator15
error with lightbulb C style inequality operator16
error with lightbulb Incomplete associations17
error Duplicate associations18
error Invalid character literal19
error Function declarations in a package cannot have a function body21
error Missing function body22
error Invalid bit string literal23
error Duplicate named associations27
error Duplicate ‘all’ -style binding for component declaration28
error Duplicate component instantiation binding29
error Duplicate component instantiation binding30
error Incorrect number of associations found in mapping32
error A positional association cannot follow after a named association33
error with lightbulb A signal cannot be the target of a variable assignment34
error with lightbulb A port cannot be the target of a variable assignment35
error with lightbulb A variable cannot be the target of a signal assignment36
error A process with a sensitivity list cannot contain any wait statements39
error Procedure declarations in a package cannot have a procedure body40
error Procedure declarations in a package body must have a procedure body41
error Generate statements must have a label42
error Instantiation statements must have a label43
error Block statements must have a label44
error Matching case statement51
error External name alias52
error with lightbulb VHDL version check53
error Duplicate declaration54
error A unary condition operator parentheses58
error duplicate enum literal69
error Invalid identifier70
error Function pureness validation76
error Missing implementation80
error with lightbulb Incorrect attribute class81
error Invalid variable assignment82
error Invalid signal assignment83
error A subprogram call cannot have an empty parameter lis86
error Unexpected tokens91
error Protected type bodies are not allowed in a package168
error Invalid use of ‘bus’ keyword171
error Invalid function parameter mode172
error Invalid variable parameter in function173
error Invalid function return type174
error Invalid deferred constant declaration175
error This declaration is not allowed in the current declarative region176
error VHDL 87 file declarations191
error Concatenation of unconstrained aggregate194
error with lightbulb Empty sensitivity list197
error with lightbulb Instantiation mismatch198
error Range wrapped inside parentheses199
error Incomplete record aggregate200
error No elements in a list201
error with lightbulb Trailing separator in a list202
error with lightbulb VHDL version check212
error with lightbulb Invalid use of return type identifiers213
error with lightbulb Conditional return statements214
error String literal is not properly closed215
error An exponent for an integer literal shall not be negative218
error Declaring the library ‘work’ is not allowed inside a context declaration219
error Referencing the library ‘work’ is not allowed inside a context declaration220, 221
error Loop variables cannot be assigned227
error Declaration not found229
error Missing full constant declaration233
error Incorrect full constant subtype234

XL Linting Rules

XL linting rules require a Sigasi Studio XL or Sigasi Studio XPRT license.

warning Null range: The left argument is strictly larger than the right1
warning with lightbulb Deprecated IEEE packages8
warning Case alternative contains redundant choices12
warning Case statement contains all choices explicitly. You can safely remove the redundant ‘others’13
warning Infinite loop. Loop is missing a wait, return or exit statement20
warning Null range: The left argument is strictly smaller than the right26
info with lightbulb Non-standard packages37
warning with lightbulb A process must either have a sensitivity list or contain one or more wait statements38
warning There has to be a whitespace before physical units47
ignore Unbound component instantiations48
warning Superfluous library clause49
warning with lightbulb Library is not available50
warning with lightbulb Find unused declarations55
warning Bitstrings may only contain std_logic metavalues57
error Duplicate design units64
warning Find unused ports67
warning Find unused generics68
warning Find dead states in state machines71
warning with lightbulb Find incomplete sensitivity lists72
warning Find superfluous signals in sensitivity lists73
warning Find dead code79
ignore Report encrypted files84
warning Find duplicate signals in sensitivity lists85
warning Detect signals and variables that are never written88
warning Detect signals and variables that are never read89
warning None or multiple matching entities for component90
warning Check naming conventions92
warning with lightbulb Incomplete port map or generic map: using defaults94
ignore Check line length97
warning Array assignment validation144
warning with lightbulb All references must have the same capitalization as their declaration163
warning Check for positional associations in instantiations164
error Invalid port associations169
error VHDL version mismatch170
warning with lightbulb Order of generic and port associations177
error with lightbulb Name mismatch178
error Unexpected return type179
error Configuration issue: Incorrect component name180
error Configuration issue: Incorrect instantiation statement label181
warning Configuration issue: Missing or incorrect binding indication182
error Configuration issue: Incorrect name in binding indication183
error Incorrect use of keyword all184
warning Redundant boolean equality check with true185
ignore Boolean equality check with false186
warning with lightbulb Check for component/entity mismatch187
ignore Header comment does not match pattern188
ignore Filename must contain primary unit name189
warning Empty loop statement190
info Entity name is a keyword in Verilog and may cause problems in mixed projects192
warning Circular compilation dependency203
error Cannot case on a type declaration209
warning Index out of range210
warning Slice has wrong direction211
error Referencing the library ‘work’ is not allowed inside a context declaration220
error with lightbulb Common Libraries version mismatch222
error with lightbulb VHDL version check223
ignore Check case of non-keywords224
warning with lightbulb re2j compatibility check225
warning Type validation226
info Whitespace in extended identifier228
ignore Sequence of operators without parentheses230
ignore Constant width vector assigned to signal231
warning Comparison of vectors with different sizes232
ignore Magic number, bitstring, or string in statement235
ignore Unconstrained signal or variable of integer type236
ignore Unexpected FSM state type237
ignore Incomplete reset branch238
ignore Deep nesting of conditional and loop statements239
ignore Unexpected keyword capitalization240
ignore Incorrect vector range direction241
ignore File contains multiple primary units242
ignore Secondary unit in unexpected file243
ignore Prohibited attribute244
ignore Prohibited keyword or operator245
ignore Prohibited package246
ignore Prohibited pragma247
ignore Prohibited library248
ignore Clock signal not used as clock249
ignore Unexpected clock edge specification250
ignore Inconsistent reset style252
ignore Multiple objects in one declaration253
ignore Inconsistent clock edge usage254

Deprecated Linting Rules

Deprecated linting rules were used by Sigasi at some point, but they’ve been removed or superseded in the most recent version.

Invalid generic listSuperseded by 20224
Invalid generic mapSuperseded by 20225
Duplicate architecture for entitySuperseded by 6431
Port map lists cannot be terminated with a ,Superseded by 20245
Port lists cannot be terminated with a ,Superseded by 20246
Signal declarations are not allowed in a process statementSuperseded by 17656
End clause validationSuperseded by 5159
Duplicate entity for librarySuperseded by 6460
Duplicate package for librarySuperseded by 6461
Duplicate configuration for librarySuperseded by 6462
Invalid use clauseRemoved as it was invalid63
Duplicate design unit in IEEERemoved as it was invalid65
Find unregistered output portsRemoved as it was invalid75
Undefined identifierSuperseded by the linker87