Verilog and SystemVerilog Linting

List of Verilog and SystemVerilog Linting Rules

The table below lists the Verilog and SystemVerilog linting rules that can be checked automatically by Sigasi. The availability of linting rules depends on the license requirements.

ST Linting Rules

ST linting rules are available for all licenses including Sigasi Studio Starter .

error Named and positional port connections cannot be mixed5
error The packed keyword is required in packed structs and unions6
error The for loop statement misses mandatory part (Verilog)9
error Parameter port list cannot be empty11
error No semicolon expected at this point (Verilog)12
error Verilog disallows empty assignments of ordered parameters (Verilog)13
error Named and positional parameter overrides cannot be mixed25
error Only one default member expression is allowed per assignment pattern29
error Only variable output ports can have a default value in non-ANSI notation33
error Only input or variable output ports can have a default value in ANSI notation34
error Duplicate formal item within the instantiated unit37
error Excessive number of actuals in ordered notation39
error Timing controls are not allowed in functions46
error Net data types must be 4-state50
error Net data types integral51
error Empty parameters53, 54
error Invalid package item55
error Unexpected preprocessor directive inside design elements57
error Non-packed member in packed structure59
error Illegal type in untagged union60
error Illegal class member access61
error Declaration not found71
error Attempted implicit declaration with default nettype none73
error Invalid enumeration element range format74
error Range of enumeration element is too large75
error Invalid construct76
error Invalid randomize argument77
error Not a value expression78
error Type not assignment compatible79
error Constraint class scope missing80
error Constraint class with packed dimensions81
error Ambiguous reference93
error Duplicate declaration95
error Invalid UDP initial value96
error Different file encoding for including file and included file102
error Missing macro identifier103
error Undefined macro104
error Forbidden macro identifier105
error Missing `endif106
error Missing identifier following expansion107
error with lightbulb Failed include108
error Macro expansion depth limit reached109
error Inclusion loop110
error Issues found while expanding macro111
error Missing macro argument list112
error Mismatched number of arguments113
error Unexpected directive operand114
error Identifier expansion with an invalid sequence of tokens115
error Unexpected conditional compiler directive116
error Unknown time literal118
error Unexpected operand119
error Missing operand120
error Unsupported include path122
error Syntax error123, 124
error Invalid macro argument list125
error Unbalanced expression126
error Unbalanced directive invocation127
error Incorect port declaration135-139
error Empty port in ANSI port list141

XL Linting Rules

XL linting rules require a Sigasi Studio XL or Sigasi Studio XPRT license.

warning Empty loops and conditional branches1
warning Check naming conventions2
ignore with lightbulb Disallow reg datatype3
info The module name is a keyword in VHDL and may cause problems in mixed language projects7
warning Case statement does not cover all cases8
warning with lightbulb Function prototype has implicit return type10
info with lightbulb Implicit subprogram port direction14
warning Default clause has to be the last item in a case statement15
error Case statement has multiple default clauses, but only one default clause is allowed16
warning File name does not match design unit17
warning File contains multiple design units18
info Parameters must have a default value19
ignore Verilog code line too long20
ignore Tabs are not allowed21
ignore File header comment does not match required pattern22
warning Named port connections have to be used for all instances with many ports24
warning Named parameter overrides have to be used for all instantiations with many parameters26
warning No event control at the top of always construct27
warning Default member must be last in assignment pattern28
warning Overwritten type key in assignment pattern30
error Duplicate member key in structure assignment pattern31
warning Mixed named and ordered notation in assignment pattern32
warning Register initialization in declarations35
warning Missing actuals for formals that have no default value38
warning Default clause missing from case statement40
error Non-blocking assignments are not allowed in functions41
warning Consecutive underscores in unit / port identifier42
warning Underscores at end of unit / port identifier43
ignore Report encrypted regions44
warning Multiple statements per line47
warning Missing bit width for parameters wider than 32 bits48
warning Named connections are not allowed with blank ports56
warning with lightbulb Regular expressions (RE2/J) compatibility check58
error Overridden method signature mismatch62-68
error Local parameter has to be initialized69
error Local parameter cannot be overridden70
error Type checking78, 79, 94, 100, 131
error Out-of-bound method signature mismatch82-92
warning Implicit net97
warning Duplicate conditions98
warning Upward reference99
warning Duplicate continuous assignments101
warning Whitespace following a backtick117
warning Invalid preprocessor syntax121
warning Unused macros128
warning Unused declaration130
warning Hidden non-virtual methods132
error Unexpected empty concatenation133
error Unexpected empty assignment pattern134
warning Duplicate port140
warning Empty port142
warning Vector as edge event expression143
ignore Implicit vector to boolean conversion144

Deprecated Linting Rules

Deprecated linting rules were used by Sigasi at some point, but they’ve been removed or superseded in the most recent version.

A Verilog net type keyword cannot be followed directly by the reg keywordSuperseded by a syntax error4
Formal item not found within the instantiated unitSuperseded by a syntax error36
Unexpected trailing , in parameter listSuperseded by the Empty parameters rule (rule 53)52
Ambiguous design unit referenceSuperseded by the more general Ambiguous reference (rule 93)72