Views


Graphical Views

Block Diagram View

[Only in Sigasi Studio XPRT]

The Block Diagram View displays a graphical view of all architectures, modules, their instantiations, and generate constructs in your current editor’s VHDL or SystemVerilog code. VHDL processes and SystemVerilog always blocks are also shown in the block diagram.

This view automatically updates while you are editing your code and offers a convenient way to visually inspect and navigate your code, even when your code is unfinished or broken.

You can open the Block Diagram View by right-clicking in the editor and selecting Show In > Block Diagram. Alternatively, in Sigasi Studio for Eclipse you can open the view via Window > Show View > Other… > Sigasi > Block Diagram and in Sigasi Studio for VS Code you can open the view via the command palette Ctrl+Shift+P and type Sigasi: Open Block Diagram.

You can also double-click blocks, ports, or wires to navigate to the corresponding HDL code. If you want to go into a block, you have to select it, right-click, and click Open Entity Declaration, Open Architecture, or Open Module.

To find an object in the Block Diagram, you can navigate from your code to the Block Diagram. In your code, right-click a signal, port, process, generate, or instantiation and select Show In > Block Diagram - just like when opening the Block Diagram View the first time. If the Block Diagram is already open, the corresponding element is highlighted, and the Block Diagram View is centered upon it.

You can export the Block Diagram View to an image with the save Save icon button. Both SVG and PNG are supported. Choose a *.svg filename for SVG export or a *.png filename for PNG export.

In Sigasi Studio for Eclipse, you can export all block diagrams of an entire project at once: Click Project > Export… > Sigasi > Block Diagrams export and select your project. All SVGs will be created within the sigasi-doc/diagrams/blockdiagrams/ folder in your project.

State Machines View

[Only in Sigasi Studio XPRT]

The State Machines View displays a graphical (bubble diagram) view of all state machines in your current VHDL or SystemVerilog editor. This viewer automatically updates while you are editing your code and offers a convenient way to visually inspect and navigate your code, even when your code is unfinished or broken.

You can open the State Machine View by right-clicking in the editor and selecting Show In > State Machines. Alternatively, in Sigasi Studio for Eclipse you can open the view via Window > Show View > Other… > Sigasi > State Machines and in Sigasi Studio for VS Code you can open the view via the command palette Ctrl+Shift+P and type Sigasi: Open State Machines Diagram.

If you have documented your state transitions (i.e., the assignments), the comments will be added as text to the transitions in the view.

You can also double-click nodes or transitions to navigate to the corresponding HDL code.

With the hide comments icon button, you can toggle the display of comments on edge labels.
With the hide conditions icon button, you can toggle the display of comments on edge labels. These labels show the code comments of the transition statements.
You also have the option to Zoom In, Zoom Out, or Zoom to Fit.

You can export state machines to an image with the save save icon button. Both SVG and PNG are supported. Choose a *.svg filename for SVG export or a *.png filename for PNG export.

In Sigasi Studio for Eclipse, you can export all state machines of an entire project at once: Click Project > Export… > Sigasi > State Machine Diagrams export and select your project. All SVGs will be created within the sigasi-doc/diagrams/statemachines/ folder in your project.

Dependencies View

The Dependencies View visualizes the dependencies of your VHDL, SystemVerilog, or mixed language projects. This view shows the relationships between your source files and makes it easy to see top levels and important packages. The Dependencies View also makes it easy to detect orphaned files.

The view is automatically updated each time you save your files.

The Dependencies View has the following options:

  • open folder icon SiStE or open folder icon SiStVSC show dependencies of the entire project. Uncheck to focus on the dependencies of the active editor only.
  • library icon SiStE or library icon SiStVSC Group design files per library
  • units icon SiStE or units icon SiStVSC Show design units inside design files. The design units are prefixed with an abbreviation of their kind architecture, module, package, …

The Dependencies View can help you navigate, too. Double-click a file name in the diagram to open the corresponding editor.

In Sigasi Studio For Eclipse, the Dependencies View can be pinned. This prevents the diagram from changing when you switch editors.

You can export this diagram for documentation by clicking the save icon.

UVM Diagram View

[Only in Sigasi Studio XPRT] ,[Only for SystemVerilog]

The UVM Diagram View displays a graphical representation of the UVM component structure through an intuitive graphical display. It visualizes the relationships between components, their hierarchical arrangement in the topology, the connections between ports, and the referenced design interfaces. The dynamic expansion of the diagram allows for efficient tracking of connections throughout the UVM component structure.

Similar to the UVM Topology View (read more about the view in Sigasi Studio For Eclipse or VS Code), this diagram offers a set of navigation options for each element (both by double-clicking on elements and through the context menu), allowing you to access element’s types, declarations, or instantiations. Double-clicking on a port connection line navigates to the corresponding connect method call in the source code.

Like other diagram views, you can find buttons on the toolbar to Zoom to Fit and export the UVM Diagram as an image (both SVG and PNG are supported).

Net Search View

[Only for VHDL]

With Net Search, you can find loads and drivers of a net. A net is defined as a signal or port and all other signals and ports that are directly connected to it. The loads are where you read the value of the net, and the drivers are where you write to this net.

To find the entire net of a signal or port, place your cursor on the identifier and right-click. Now select Find Net. Alternatively, you can press CTRL+SHIFT+H.

The Net Search View will appear. For big designs, it might take a while before the results appear.

From the Net Search View, you can navigate to the VHDL code by double-clicking the search results.