The Sigasi 2.23 release introduces basic datatype checking at type-time for VHDL; improved Verilog support; and much more.
Basic datatype checking at type-time for VHDL
Sigasi now reports datatype violations while you type (at type-time). You don't have to wait for your simulator to report datatype errors. Whenever you write a wrong datatype, you see an error message within less than a second! Screencast : Datatype checks while you type
Improved Verilog support
We are accelerating our development of the Verilog version: Open Module Declaration by CTRL+clicking on instantiation Hover on module name to see the inline documentation
Other new and noteworthy improvements
- Improved support for external VHDL files (i.e. non Sigasi Project VHDL files). We now report all syntax errors.
- Linting check for read/write access of port, signal, generic and constant declarations [Premium]
- Updated the JAVA Virtual Machine in the stand-alone to version 8. Note that this is not updated with the Sigasi update mechanism; you need a fresh download if you want this improvement.
- Support for Eclipe Luna
- Added VHDL Project Import Wizard
- Better error reporting in unknown instantiations: only mark the unknown component name as a single error
- Added tutorial project for Sigasi Premium
- Added preference page to configure Task Tags in comments (TODO, FIXME)
- Added Quickfix for XilinxProcessorIP Libraries in xilinx ISE
- Export Block Diagram and State Machine graphics to PNG images [Premium]
- Dead-code linting in if statements [Premium]
- Update Xtext dependency to 2.6.1
- ticket 2883 : Vmap should never make changes in wrong modelsim.ini file
- ticket 2893 : Case statement analysis should not fail on if expression inside parenthesis
- ticket 2798 : Scoping bug in record field in result of overloaded function call
- ticket 2848 : scoping problem in when/else assignment
- ticket 2921 : Loading a FlexNet license should never block the UI